Exemplary embodiments of this invention relate to dynamic storage, and particularly to dynamically and independently managing dynamic storage.
Substantially all modern computers and other digital systems rely on semiconductor memory devices to store data and instructions for processing by a central processing unit (CPU). Most of these systems have a system memory, which usually consists of dynamic random access memory (“DRAM”) devices. The memory storage cost/bit of DRAM devices is relatively low because a DRAM memory cell needs relatively few circuit components to store a data bit as compared with other types of memory cells, such as static random access memory (“SRAM”) devices. Thus, a high capacity system memory can be implemented using DRAM devices for a relatively low cost.
Although DRAM devices have the advantage of providing relatively low-cost data storage, they also have the disadvantage of consuming significant power. In fact, DRAM devices used in a digital system, such as a computer, can consume a significant percentage of the total power consumed by the system. The power consumed by computers and other digital systems can be a critical factor in their utility in certain applications.
One operation that tends to consume power at a substantial rate is refreshing memory cells in a DRAM device. As is well known in the art, DRAM memory cells, each of which essentially consists of a transistor (NFET) and a capacitor, must be periodically refreshed to retain data stored in the DRAM device. This refreshing is typically performed by activating each row of memory cells in an array, which essentially involves reading data bits from the memory cells in each row and then internally writing those same data bits back to the same cells in the row.
Refreshing is generally performed at a rate needed to keep charge stored in the memory cells that represents their logic state from leaking away between refreshes. Since refreshing involves accessing data bits in a large number of memory cells at a rapid rate, refreshing tends to be a particularly power-hungry operation. Thus, many attempts to reduce power consumption in DRAM devices have focused on reducing the rate at which power is consumed during a refresh operation. For example, a typical memory cell includes a transistor coupled to a storage element, typically a capacitor. Each memory cell stores a bit (i.e., a logic 1 or a logic 0) of the data. The memory cells are arranged in a matrix of addressable rows and columns, with each row corresponding to a multi-bit word of data. The bit of data in each memory cell is stored on the capacitor as charge, or lack thereof. This data must be refreshed because the charge of the capacitor leaks over time—the data retention time of the cell. In order to prevent the loss of data, the data stored in the memory cell must be refreshed before the end of the data retention time. It follows then that the faster the charge leaks from the memory cell, the higher the data refresh rate that is required for the cell.
The amount of power consumed by a refresh operation also depends on which of several refresh modes is active. A self-refresh mode is normally active during periods when data is not being read from or written to the DRAM device. Since many electronic devices, such as notebook computers, are often inactive for substantial periods of time, the amount of power consumed during a self-refresh operation can be an important factor in determining how long the electronic device can be used after a battery charge. While power is also consumed at a significant rate during other refresh modes when the DRAM device is active, the DRAM device is consuming power at a significant rate anyway while the data stored therein is being accessed. Therefore, if the power consumption during a self-refresh operation is reduced, the overall rate of power consumption is reduced.
One technique that has been used to reduce the amount of power consumed by refreshing DRAM memory cells is to vary the refresh rate as a function of temperature. As is well known in the art, the rate at which charge leaks from a DRAM memory cell increases with temperature. The refresh rate must be sufficiently high to ensure that no data is lost at the highest temperature in the specified range of operating temperatures of the DRAM device. Yet, DRAM devices normally operate at temperatures that are substantially lower than their maximum operating temperatures. Therefore, DRAM devices are generally refreshed at a rate that is higher than the rate actually needed to prevent data from being lost, and, in doing so, unnecessarily consume power. To address this problem, some commercially available DRAM devices allow the user to program a mode register to select a lower maximum operating temperature. The DRAM device then adjusts the refresh rate to correspond to the maximum operating temperature selected by the user. Although adjusting the refresh rate to correspond to a lower maximum operating temperature does reduce the rate of power consumed during a refresh operation, it nevertheless still allows power to be consumed at a significant rate. If the refresh rate was reduced beyond a safe limit, at least some of the memory cells might not be refreshed before that data stored therein was lost. Data subsequently read from the DRAM device would then contain erroneous data bits.
It should be understood, moreover, that the availability of the DRAM is impacted by the frequency of the refresh operation. When the DRAM is being refreshed, data can neither be retrieved from the macro nor written into the macro.
It is therefore desirable to have a method, system, and apparatus that reduces the power consumed by a DRAM device during a refresh of the DRAM and increases the DRAM availability.